Analyzing Behavior of Less Interrupt Overhead Architecture for Effective Cache Utilization

Hardware and software interrupts negatively affect system performance primarily because of pipeline flushing and pollution of TLBs and caches. The architecture that causes fewer traps and enhances cache efficiency is worth achieving. We propose the novel approach to reduce the number of traps caused by system calls and enhance cache efficiency. In this approach, effective cache utilization can be achieved with exception-less system calls and the thread management with continuations in system call processing. We implemented this architecture, and evaluated the effect.