Title :
Simulated annealing for folding of programmable logic arrays
Author :
Sanchez, Jose Manuel ; Ballesteros, Joaquin
Author_Institution :
Dept. de Inf. y Autom., Univ. Complutense, Madrid
fDate :
3/14/1994 12:00:00 AM
Abstract :
Addresses the multiple column folding using a methodology using the SA algorithm. First of all, the multiple unconstrained column folding is studied. Then the SA algorithm for solving several constrained folding problems is used and the simple folding is considered as a special case of a constrained folding
Keywords :
VLSI; logic arrays; logic design; simulated annealing; SA algorithm; constrained folding problems; multiple column folding; multiple unconstrained column folding; programmable logic arrays;
Conference_Titel :
Synthesis and Optimisation of Logic Systems, IEE Colloquium on
