• DocumentCode
    3571752
  • Title

    Real-time scheduling for nested-parallel task model on multi-core processors

  • Author

    Lokhande, Mahesh ; Atique, Mohammad

  • Author_Institution
    Dept. of Comput. Sci. & Eng., P.I.E.T., Nagpur,India, P.I.E.T., Nagpur, India
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    7
  • Abstract
    In today´s scenario, lots of real-time applications are encountered which includes numerous computations that have to be done in parallel in stipulated period of time. For such tasks single core processors cannot perform well even multiprocessors are not able to, because traditionally, sequential models were used which ignore parallelism between the tasks. However, parallel models have the capability to parallelize specific segments of tasks, thereby leading to shorter response times as possible. In this paper, the problem of scheduling the real time, periodic, implicit deadline nested-parallel tasks on multi-core processors is discussed. Initially, a nested-parallel task model, which is synchronous in nature wherein each task consists of number of segments and each segment consists number of parallel or nested threads, is considered. After, a novel task disintegration technique that disintegrates each parallel or nested-parallel task into a set of sequential tasks is proposed. Here it is proved that the proposed task disintegration technique achieve a resource augmentation bound of 3.414 when scheduled disintegrated tasks using global EDF scheduling, which means, if any task set is feasible on m unit speed processors, it can be scheduled using proposed technique on m 3.414 times faster processors.
  • Keywords
    multi-threading; multiprocessing systems; parallel processing; processor scheduling; global EDF scheduling; implicit deadline nested-parallel task model; multicore processors; nested threads; parallel threads; periodic scheduling; real time scheduling; real-time applications; resource augmentation bound; sequential tasks; task disintegration technique; task set; unit speed processors; Computational modeling; Computers; Instruction sets; Mathematical model; Parallel processing; Silicon; Scheduling; multi-core processors; nested-parallel tasks; resource augmentation bound; task disintegration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical, Computer and Communication Technologies (ICECCT), 2015 IEEE International Conference on
  • Print_ISBN
    978-1-4799-6084-2
  • Type

    conf

  • DOI
    10.1109/ICECCT.2015.7226048
  • Filename
    7226048