A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects

Author

Lu, J.-Q. ; Kwon, Y. ; Rajagopalan, G. ; Gupta, M. ; McMahon, J. ; Lee, K.-W. ; Kraft, R.P. ; McDonald, J.F. ; Cale, T.S. ; Gutmann, R.J. ; Xu, B. ; Eisenbraun, E. ; Castracane, J. ; Kaloyeros, A.

Author_Institution

Focus Center-New York, Rensselaer Polytech. Inst., Troy, NY, USA

fYear

2002

fDate

6/24/1905 12:00:00 AM

Firstpage

78

Lastpage

80

Abstract

A viable approach for a monolithic wafer-scale three-dimensional (3D) IC technology platform is presented, focusing on wafer bonding, wafer thinning and inter-wafer damascene-patterned interconnects. Principal results include successful wafer alignment, wafer bonding with both BCB and Flare, post bonding wafer thinning using grinding and polishing to 35-50 μm, and via etch through the required material stack.

Keywords

copper; etching; integrated circuit interconnections; polishing; wafer bonding; 35 to 50 micron; BCB; Cu; Cu damascene patterned interconnects; Flare; dielectric bonding glues; grinding; inter-wafer interconnects; monolithic IC technology; polishing; via etch; wafer alignment; wafer bonding; wafer thinning; wafer-scale 3D IC technology platform; Copper; Costs; Dielectrics; Etching; Optical device fabrication; Packaging; Planarization; Testing; Three-dimensional integrated circuits; Wafer bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International

Print_ISBN

0-7803-7216-6

Type

conf

DOI

10.1109/IITC.2002.1014893

Filename

1014893