FPGA Implementation of a 3/spl times/3 window median filter based on a new efficient bit-serial sorting algorithm

In this paper, we proposed a new efficient bit-serial sorting algorithm for an implementation of 3/spl times/3 window median filter. The proposed algorithm is based on a majority concept in determining the bits of the median value. The majority function is implemented by an optimized nine-bit sorting network, which is more efficient than the existing ones. The algorithm was implemented by VHDL and graphical environment in MAX+PlusII of ALTERA. The simulation results indicate that the circuit is capable of running at 37.59 MHz and is composed of 462 logic cells.