DocumentCode
3571932
Title
Technology and Design Challenges of MOS VLSI
fYear
1981
Firstpage
9
Lastpage
23
Abstract
It is the purpose of this paper to explore some of the technological advances, apart from lithography, which will be required in MOS during the next decade. Feature size is an imperfect measure of technological sophistication, but it is universally understood, and will be used in this paper as a technology indicator. However, many technological advances besides lithography were required to scale MOS technology from 10 μm to 2.5 μm; the change from metal-gate PMOS to self-aligned Si-gate NMOS being the best example. And comparable technological advances will be required during the next decade to scale from 2.5 μm to 0.5 μm. This paper deals with these advances.
Keywords
Circuit synthesis; Computer industry; Instruments; Laboratories; Lithography; MOSFETs; Physics; Production; Transistors; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Circuits Conference, 1981. ESSCIRC '81. 7th European
Print_ISBN
3800712385
Type
conf
Filename
5435017
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