Title :
Optimized Scaled LOCOS Isolation Scheme for 0.25 μm CMOS
Author :
Meyssen, V.M.H. ; Velghe, R.M.D.A. ; Montree, A.H.
Author_Institution :
Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands.
Abstract :
In this paper, a scaled LOCOS isolation scheme with optimized oxidation stack and reduced field oxide thickness, is presented for 0.25 μm design rules. With this scaled LOCOS isolation technology, short bird´s beak encroachment, limited field oxide thinning, high punch-trough voltage and low leakage current have been achieved by simple fabrication processes.
Conference_Titel :
Solid State Device Research Conference, 1995. ESSDERC '95. Proceedings of the 25th European
