Architecture and implementation of a vector MAC unit for complex number

Signal processing requires high performance digital signal processors(DSP) and hardware accelerators. Real and complex multiply-accumulate(MAC) units are the most critical computation units in the DSPs and accelerators, which greatly impact the performance, power and chip area of the signal processing system. A fixed-point Single-Instruction-Multiple-Data(SIMD)/vector MAC architecture is presented in this paper. It supports 8-bit/16-bit/32-bit real and complex MAC operations. The proposed vector MAC unit can be fully pipelined. Compared to normal real MAC unit, the proposed vector MAC unit needs to double the resources. For the computation of real and imaginary parts, the operand muxing and extra carry-save adders(CSA) are all required to ensure a correct result. The "shared segmentation" and "shared subtree" methods can be applied to share the circuit among 8-bit, 16-bit and 32-bit operations.