Power reduction technique using adiabatic logic

This paper presents the implementation of a 4-bit serial in serial out (SISO) shift register and a 2-to-1 multiplexer using Complementary Energy Path Adiabatic Logic (CEPAL). This static adiabatic logic has proved its advantage through the minimization of the l/2CV_dd² energy dissipation occurring every cycle. Firstly, the performance characteristics of CEPAL basic gates are compared against the conventional static CMOS logic counterpart to identify its adiabatic power advantage. The basic gates - NOT, NAND, NOR, XOR have been simulated. Finally a 4-bit serial in serial out (SISO) shift register is implemented with both the technologies and comparisons have been made. The analysis is carried out using the industry standard EDA design environment using 250 nm technology libraries from Tanner. The results prove that the CEPAL shift register is 76% more power efficient than the CMOS shift register at 100MHz and at 2.5V operating voltage.