Analyzing the Optimal Voltage/Frequency Pair in Fault-Tolerant Caches

When the processor works at very-low voltages to save energy, failures in SRAM cells increase exponentially at voltages below VCC_min. In this context, current SRAM-error detection and correction proposals incur on a significant performance penalty since they increase access latency and disable cache lines that cannot be corrected, so decreasing the effective cache capacity. This reduction implies more cache misses, so enlarging the execution time which, contrary to expected, can turn in higher energy consumption. This paper characterizes SRAM failures at very-low voltages and presents an evaluation methodology to analyze the impact on energy consumption of error correction approaches. To do so, several voltage/frequency pairs are studied and the optimal pair is identified from an energy point of view. To focus the research, experimental results have been obtained for the recently proposed fault-tolerant HER cache. Results show that, for a 32nm technology node, the voltage/frequency pair of 0.45V/800MHz, which induces by 31% SRAM failure rate, provides the lowest overall energy consumption (by 62% energy savings compared to a non-faulty conventional cache).