Simultaneous Optical Path-Setup for Reconfigurable Photonic Networks in Tiled CMPs

This paper proposes a tiled chip multiprocessor (CMP) architecture built around an all-optical reconfigurable network, thought to significantly reduce path-setup latency and energy consumption. We propose a novel optical path-setup procedure that is able to configure multiple optical switches simultaneously. Our architecture uses a simple ring-based path-setup network for assisting an optical folded Torus Network-on-Chip (NoC) serving cache coherence traffic. We investigate performance/power effects on a CMP system and we compare against both a high-performance electronic folded Torus NoC (electronic baseline) and a state-of-the-art optical folded Torus with sequential path-setup (optical baseline). The reduced path-setup overhead of our proposal allows reconfigurable optical networks to potentially be compatible with the small messages composing directory-based cache coherent traffic and thus be the enabling factor for significantly improving energy consumption.