"CERE": A CachE Recommendation Engine: Efficient Evolutionary Cache Hierarchy Design Space Exploration

Design Space Exploration is a critical step in chip design. Unfortunately, it takes significant amounts of time and resources to explore a fraction of the design space. Herein, we present a heuristic, evolutionary approach (Genetic Algorithm) to exploration that significantly cuts down on the time and resources, obtaining a near optimal design. We demonstrate the real-world utility of our tool-chain "CERE" by rapidly and efficiently designing the cache hierarchy which maximizes the performance of a web-browser navigating to a set of famous websites running on a single ARM core. We rapidly traverse 134,136 possible configurations. At about two days per simulation on the Gem5 full system simulator, the entire space would have taken 268,272 CPU-Days or ≃734 CPU-Years (≃3.7 Years on a cluster of a hundred dual core machines) to brute force search. "CERE" provided results in ≃4.5 days and used ≃17.5 CPU-Days on our cluster. We ran the configurations that "CERE" chose through Gem5 to verify that "CERE" made the right choices and we were able to observe a 17.1% speedup going from the "best" hierarchy relative to the "Worst" hierarchy.