Deadline-Aware Interrupt Coalescing in Controller Area Network (CAN)

The introduction of virtualized multi-core processors in automotive embedded systems opens up opportunities like safe consolidation of previously distributed electronic control units (ECUs) on a shared platform. On the other hand, challenges arise in areas like I/O processing due to overheads experienced in virtualized environments. Designs of I/O controllers have to be adjusted to allow efficient, scalable, and real-time capable communication under these circumstances. Interrupts are an essential part in real-time communication. However, they introduce significant computational overheads, because they force multiple context switches within the CPU. Interrupt coalescing reduces the burden of interrupt processing by merging multiple interrupts within the I/O hardware. However, existing coalescing approaches are not feasible for real-time networks like CAN due to the latencies they introduce. In this paper, we introduce a deadline-aware approach of interrupt coalescing for CAN controllers. It minimizes the amount of interrupts forwarded while guaranteeing the systems real-time capability. We provide three approximations of the method, which can be implemented in hardware. We evaluate the reduction of interrupts that can be achieved with each approach and determine the hardware cost with a prototypical FPGA implementation.