A Process for the Detection of Design-Level Hardware Trojans Using Verification Methods

Hardware Trojans have emerged as a serious threat the past years. Several methods to detect possible hardware Trojans have been published, most of them aiming at detection during post-fabrication tests. Nevertheless, hardware Trojans are more probable to be inserted at design-level, as resources required to do so are much lower than those at fabrication. At design-level, verification methods have been shown to serve for Trojan detection. In this paper, we propose a design process to utilize verification methods in hardware Trojan detection, being able to be integrated into a state-of-the-art design flow for embedded systems. We outline the fundamental basics of verification methods and go then into the details of each step in the process. We identify assets and attackers, and outline which methods are suited to defend against which type of attack.