Execution condition analysis in high level synthesis: a unified approach

The degree of conditional hardware reuse achieved after a high-level synthesis process depends on two factors: the number of mutually exclusive (m.e.) operation pairs that an algorithm can detect and the description style used by the designer when specifying the system. In this paper, we propose a method that deals with both aspects. Firstly, it includes a mechanism to analyze the input description and to identify all the m.e. operation pairs in a simple and homogeneous way, independently of the conditional constructs (IF of CASE) used to specify the control flow to the system. Secondly, it provides a collection of formal transformations on the input description which produces a specification of the same behavior that leads to an improved implementation n terms of the degree of conditional reuse that is achieved