A novel approach to design complex multiplier using vedic sutras

Multiplication of complex numbers finds numerous applications in science and engineering. At the implementation level, the parameters affecting the performance are speed, area and power consumption. Hence, an attempt is made in this paper to improve the speed of complex multiplier by using Vedic mathematical techniques. Vedic mathematics contains 16 sutras which are mathematical short hands for range of operations covering basic arithmetic, algebraic and trigonometric operations to more complex calculus operations. Traditionally, the complex multiplier suffers from low speed due to more number of partial product generations and carry propagation. Out of 16 sutras only two sutras are used for multiplication, i.e. one for general case, and another for special case. The proposed system is designed around the general case multiplication sutra. The modeling of the solution is done using the Simulink block sets and functional verification is performed using Xilinx ISE tool.