Low power MAC architecture for DSP applications

Multiply and Accumulate is the main component of the DSP System, which is the major block for power consumption and decides the speed of the overall system due to its complex operation. Hence in most of the DSPs, it lies in the critical path. In this work, Low power MAC architecture has been proposed by examining the critical paths and the hardware complexities. Proposed is a generic architecture which can extended to n bit width. The designs were implemented using ASIC design methodology by synthesizing in Cadence RTL compiler and mapped to TSMC 65nm technological library cells. The results show that the proposed architecture for 8-bit, reduces Leakage power consumption of MAC unit by 24.27 % The proposed concept for a 8-bit MAC unit was also proved in the FPGA domain.