A technology mapping algorithm for PAL-based devices using multi-output function graphs

Author

Kania, Dariusz

Author_Institution

Inst. of Electron., Silesian Univ. of Technol., Gliwice, Poland

Volume

1

fYear

2000

fDate

2000

Firstpage

146

Abstract

The objective of the technology mapping method presented in this paper is to cover a multiple-output function by a minimal number of PAL (programmable array logic) based logic blocks included in CPLDs (complex programmable logic devices). According to this method, product terms included in a logic block can be shared by several functions. The developed algorithms, implemented within the PALDec system, have been used for partitioning the benchmark circuits due to implementation by means of the PAL-based logic blocks with the restricted number of terms. The results are compared to the classical technology mapping method and synthesis of benchmarks executed by means of MACHXL and MAX+PLUS II software

Keywords

graph theory; logic CAD; logic partitioning; programmable logic arrays; technology CAD (electronics); MACHXL software; MAX+PLUS II software; PAL-based devices; PAL-based logic blocks; PALDec system; benchmark circuit partitioning; benchmark synthesis; complex programmable logic devices; multi-output function graphs; programmable array logic; shared product terms; technology mapping algorithm; Boolean functions; Circuit synthesis; Data structures; Digital circuits; Logic circuits; Logic devices; Logic functions; Minimization methods; Optimization methods; Partitioning algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Euromicro Conference, 2000. Proceedings of the 26th

Conference_Location

Maastricht

ISSN

1089-6503

Print_ISBN

0-7695-0780-8

Type

conf

DOI

10.1109/EURMIC.2000.874627

Filename

874627