A novel approach to minimising the logic of combinatorial multiplexing circuits in product-term-based hardware

An innovative technique for logic minimisation of combinatorial multiplexing circuits is introduced. It is targeted at product-term (PT) based hardware, like PAL (programmable array logic), PLAs (programmable logic arrays) and CPLDs (complex programmable logic devices), though its usage is not limited to such hardware The technique exploits the fact that, sometimes, circuit designers have no interest in unequivocally specifying the particular encoding of selected control words in a multiplexer, provided that there is a unique correspondence between selected words and multiplexer inputs. Our approach enables a HDL (hardware description language) compiler to pick a particular encoding of the selected words that favours logic minimisation the most. We have developed a prototype of an optimisation algorithm based on simulated annealing, which targets circuits implemented in a PT-based functional unit of a reconfigurable processor. Benchmark results show that a considerable reduction in logic (up to ~46% in the number of PTs utilised, for the circuits studied) can be achieved