DocumentCode :
357677
Title :
Parameterized reusable component library methodology
Author :
Shelar, Rupesh S. ; Nath, Sacheendra ; Nanaware, Jagmohan S.
Author_Institution :
Micro-archit. Group, Silicon Autom. Syst., Bangalore, India
Volume :
1
fYear :
2000
fDate :
2000
Firstpage :
410
Abstract :
The authors describe the Parameterized Reusable Component Library (PRCLIB) methodology, which supports design reuse automation. Unlike the Y-chart approach (A.C.J. Kienhuis, 1998) which helps design space exploration at higher levels of abstraction, PRCLIB methodology addresses the issue of design space exploration at RTL levels. Although the methodology is developed keeping in mind Data Driven Media Processor (DDMP), the methodology is applicable to general purpose processors as well. In PRCLIB methodology, we also support parameterized test pattern generation, intellectual property (IP) reuse, automatic RTL code generation. Finally, we compare the scope of our tool with a similar tool, Hyper (O. Bentz)
Keywords :
automatic test pattern generation; circuit CAD; design engineering; industrial property; program compilers; software libraries; DDMP; Data Driven Media Processor; Hyper; PRCLIB methodology; RTL levels; Y-chart approach; automatic RTL code generation; design reuse automation; design space exploration; general purpose processors; intellectual property reuse; parameterized reusable component library methodology; parameterized test pattern generation; space exploration; Automatic test pattern generation; Design automation; Design methodology; Image processing; Intellectual property; Libraries; Signal processing; Silicon; Space exploration; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Euromicro Conference, 2000. Proceedings of the 26th
Conference_Location :
Maastricht
ISSN :
1089-6503
Print_ISBN :
0-7695-0780-8
Type :
conf
DOI :
10.1109/EURMIC.2000.874660
Filename :
874660
Link To Document :
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