IP reuse VLSI architecture for low complexity fast motion estimation in multimedia applications

A novel intellectual property (IP) VLSI architecture for the implementation of real time and low complexity fast motion estimation for multimedia applications is proposed. The motion estimation is a key issue either in H.263/MPEG video coding or in image filtering. Specifically, the algorithms based on the predictive spatio-temporal technique achieve high coding quality at reasonable computational power by exploiting the spatio-temporal correlation of the video motion field. The novel architecture, obtained by a design reuse methodology, is parametric and configurable and hence it allows for the implementation of different predictive algorithms. It also features hardware complexity scalability and it is suitable for the design of ASICs optimized for a wide range of multimedia applications. The IP, synthesized for a 0.25 μm CMOS technology, achieves a computational power up to 740×10 ⁶ absolute differences per second, for a maximum 0.96 mm² core size, and permits the processing of typical video images at clock frequencies of a few MHz