Title :
Disturbance-suppressed ReRAM write algorithm for high-capacity and high-performance memory
Author :
Dae Seok Byeon ; Chi-Weon Yoon ; Hyun-Kook Park ; Yong-Kyu Lee ; Hyo-Jin Kwon ; Yeong-Taek Lee ; Ki-Sung Kim ; Yong-Yeon Joo ; In-Gyu Baek ; Young-Bae Kim ; Jeong-Dal Choi ; Kye-hyun Kyung ; Jeong-Hyuk Choi
Author_Institution :
Samsung Electron., Hwasung, South Korea
Abstract :
In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test array. Based on the analysis, disturbance-suppressed ReRAM write algorithm is proposed to prove the feasibility of future high-capacity and high-performance ReRAM memory for NAND applications. By appropriately controlling WL and BL bias, surge current that causes write disturbance is successfully suppressed so that the overall cell distribution was narrowed down by more than 70%.
Keywords :
NAND circuits; flash memories; integrated circuit testing; logic testing; resistive RAM; BL bias; NAND applications; ReRAM memory; WL bias; bit-line bias; cell distribution; disturbance-suppressed ReRAM write algorithm; surge current; test array; word-line bias; Capacitance; Surges; Switches; 3D-Stack; Cross-point; Emerging memory; High density; Multi-bit cell; NAND Application; ReRAM; Resistive switching; Scaling limit; Write Disturbance;
Conference_Titel :
Non-Volatile Memory Technology Symposium (NVMTS), 2014 14th Annual
Print_ISBN :
978-1-4799-4203-9
DOI :
10.1109/NVMTS.2014.7060837
