Title :
A world´s first product of three-dimensional vertical NAND Flash memory and beyond
Author :
Ki-Tae Park ; Dae-Seok Byeon ; Doo-Hyun Kim
Author_Institution :
Flash Design Team, Samsung Electron. Co. Ltd., Hwaseong, South Korea
Abstract :
In this work, we present a 3D 128Gb 2bit/cell vertical-NAND (V-NAND) Flash product. The use of barrier-engineered materials and gate all-around structure in the 3D V-NAND cell exhibits advantages over 1xnm planar NAND, such as small Vth shift due to small cell coupling and narrow natural Vth distribution. Also, a negative counter-pulse scheme realizes a tightly programmed cell distribution. In order to reduce the effect of a large WL coupling, a glitch-canceling discharge scheme and a pre-offset control scheme is implemented. Furthermore, an external high-voltage supply scheme along with the proper protection scheme for a high-voltage failure is used to achieve low power consumption. The chip accomplishes 50MB/s write throughput with 3K endurance for typical embedded applications. Also, extended endurance of 35K is achieved with 36MB/s of write throughput for data center and enterprise SSD applications. And 2nd generation of 3D V-NAND opens up a whole new world at SSD endurance, density and battery life for portables.
Keywords :
NAND circuits; failure analysis; flash memories; integrated circuit reliability; 3D V-NAND cell; 3D V-NAND flash product; SSD endurance; WL coupling; barrier-engineered materials; battery life; data center; enterprise SSD application; extended endurance; external high-voltage supply scheme; gate all-around structure; glitch-canceling discharge scheme; high-voltage failure; low-power consumption; narrow natural threshold voltage distribution; negative counter-pulse scheme; planar NAND; pre-offset control scheme; protection scheme; small-cell coupling; three-dimensional vertical NAND flash memory; tightly-programmed cell distribution; typical embedded application; write throughput; Computer architecture; Couplings; Flash memories; Logic gates; Microprocessors; Performance evaluation; Three-dimensional displays; 3D Vertical NAND Flash; Gate stack; WL crosstalk reduction; enterprise application; external high voltage supply; good endurance; high performance; negative counter-pulse; solid-state drive;
Conference_Titel :
Non-Volatile Memory Technology Symposium (NVMTS), 2014 14th Annual
Print_ISBN :
978-1-4799-4203-9
DOI :
10.1109/NVMTS.2014.7060840