Title :
Power optimization for pipelined ADC design
Author :
He Tang ; Hai Wang ; Hui Zhao
Author_Institution :
Sch. of Microelectron. & Solid-State Electron., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
This paper proposes an optimization method focusing on releasing the power limitation by stage partition and the ratio of MDAC´s op-amp power to comparator power (Pop-amp/Pcomp). This optimization method has been verified by a 10-bit pipelined ADC under TSMC 65nm CMOS process.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; comparators (circuits); operational amplifiers; MDAC op-amp power-comparator power ratio; TSMC CMOS process; pipelined ADC design; power limitation; power optimization; size 65 nm; stage partition; TV; optimization; pipelined ADC; power ratio; stage partition;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
DOI :
10.1109/EDSSC.2014.7061087
