A improved frontend for high-speed SHA-less pipelined ADC

Author

Lili Xu ; Chenchen Zhao ; Fule Li ; Chun Zhang ; Zhihua Wang

Author_Institution

Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China

fYear

2014

Firstpage

1

Lastpage

2

Abstract

This paper presents an improved frontend directed at a 14-bit 250MS/s pipelined analog-to-digital converter (ADC) in 180nm CMOS process. A SHA-less structure is introduced to reduce power consumption and noise. And a new timing strategy is proposed to address its disadvantages. It matches the signal path between comparators and MDAC in the first stage by combining the timing sequence with high-speed dynamic comparators. As a result, it minimizes the aperture error without reducing tracking time or amplifying time of multiplying digital-to-analog converter (MDAC). A comparator offset calibration technology is also used to accommodate larger aperture error. Simulation with transient noise shows 75.9 dB SNDR and 91.38 dB SFDR at 30 MHz input frequency. And the power consumption is 67mW at 1.8V supply.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; comparators (circuits); pipeline arithmetic; CMOS process; MDAC; SFDR; SHA-less pipelined ADC; SNDR; comparator offset calibration technology; frequency 30 MHz; high-speed dynamic comparators; multiplying digital-to-analog converter; pipelined analog-to-digital converter; power 67 mW; sample and hold amplifier; size 180 nm; voltage 1.8 V; CMOS integrated circuits; Calibration; Switches; Timing; SHA-less; offset calibration; pipelined ADC; timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on

Type

conf

DOI

10.1109/EDSSC.2014.7061089

Filename

7061089