A dual channel 10-b pipelined ADC for Intelligent Transport System

Author

Ghil-Geun Oh ; Seung-Tak Ryu

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea

fYear

2014

Firstpage

1

Lastpage

2

Abstract

This paper describes a 10 b 40 MS/s dual channel pipelined ADC that is suitable for Intelligent Transport System (ITS). For proper operation in severe environment of vehicle, a dual-channel ADC core shares a band-gap (BGR) and current reference circuits. Also, the internal signal range amplification method extends the error correction range of the ADC, and the LDO-referencing technique reduces the circuit complexity by eliminating reference drivers. A 10 b ADC is implemented in a 180 nm CMOS process and achieves 59.3 dB SNDR and 74.9 dB SFDR at Nyquist input. Measured DNL/INL are -0.17/0.22 LSB and ±0.25 LSB, respectively. ADC consumes 42.44 mW at 3.3 V/1.8 V supplies.

Keywords

CMOS integrated circuits; analogue-digital conversion; automotive electronics; circuit complexity; electronic engineering computing; integrated circuit noise; intelligent transportation systems; reference circuits; road vehicles; BGR; CMOS process; ITS; LDO-referencing technique; Nyquist input; SFDR; SNDR; analogue-digital conversion; band-gap; circuit complexity; current reference circuits; dual channel pipelined ADC core; error correction range; intelligent transport system; internal signal range amplification method; power 42.44 mW; reference drivers; size 180 nm; vehicle; Process control; Radio frequency; BGR; Intelligient Transport System (ITS); LDO; internal signal amplification; pipelined ADC; temperature coefficient;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on

Type

conf

DOI

10.1109/EDSSC.2014.7061090

Filename

7061090