DocumentCode
3578030
Title
Design of a high resolution multi-phase clock generator based on DLL
Author
Yu Qi ; Chang Yang ; Jing Li ; Shuangyi Wu ; Ning Ning
Author_Institution
State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fYear
2014
Firstpage
1
Lastpage
2
Abstract
This paper presents a multi-phase clock generator with high resolution based on DLL. By employing the static phase error, fine tuning step is achieved with the simplest DLL structure. The charging current and discharging current of charge pump (CP) are set to be unequal to get static phase error. The simulation results show the delay step resolution of the generator with 400MHz input is 5ps and the control voltage (VC) is 0.5V when DLL is locked.
Keywords
charge pump circuits; clocks; delay lock loops; integrated circuit design; DLL structure; charge pump; delay-locked loop; fine tuning; frequency 400 MHz; high resolution multiphase clock generator; static phase error; voltage 0.5 V; Clocks; Computer architecture; Delays; Generators; Microprocessors; Partial discharges; Voltage control; DLL; high resolution; static phase error;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
Type
conf
DOI
10.1109/EDSSC.2014.7061106
Filename
7061106
Link To Document