Area-efficient recursive degree computationless modified Euclid´s architecture for Reed-Solomon Decoder

This paper proposes a high-speed low-complexity simplified recursive degree computationless modified Euclid´s (SrDCME) architecture for the Reed-Solomon Decoder. The area-efficiency of the proposed architecture is obtained by replacing the conventional systolic architecture with a recursive architecture that uses a single processing element. The hardware complexity was further reduced by merging the redundant data paths and introducing new control mechanism. The critical path delay of the proposed SrDCME requires only T_Mult+T_ADD and the latency is 4t²-2t which is the lowest compared with previous recursive architectures. The proposed SrDCME architecture has been implemented with 0.13-μm CMOS technology and the synthesized results show that it requires about 24.2% fewer gates than the latest area-efficient design.