A 40Gbps quarter rate CDR using CMOS-style signal alignment strategy in 65nm CMOS

Author

Peng Wang ; Xuqiang Zheng ; Ziqiang Wang ; Chun Zhang ; Zhihua Wang

Author_Institution

Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China

fYear

2014

Firstpage

1

Lastpage

2

Abstract

This paper presents a 40Gbps quarter rate clock and data recovery (CDR) based on phase interpolator (PI) in 65nm CMOS. Quarter rate architecture is adopted to relax bandwidth requirement. A CMOS-style signal-alignment strategy is proposed to implement 8:32 demultiplexer (Demux) block, achieving 30.9% system power reduction. CDR can track maximum ±488.3ppm frequency offset between transmitter and receiver. Simulation shows that peak-to-peak jitter generation is 827.2fs. CDR consumes 159mW from 1V supply and takes an area of 0.21 mm².

Keywords

CMOS integrated circuits; clock and data recovery circuits; clocks; demultiplexing equipment; CMOS-style signal alignment strategy; PI; bit rate 40 Gbit/s; clock and data recovery; demultiplexer block; demux block; peak-to-peak jitter generation; phase interpolator; power 159 mW; quarter rate CDR; receiver; size 65 nm; time 827.2 fs; transmitter; voltage 1 V; CMOS integrated circuits; Ice; Latches; CDR; CMOS-style signal alignment strategy; Demux; PI;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on

Type

conf

DOI

10.1109/EDSSC.2014.7061137

Filename

7061137