A flash ADC based on VCO-based comparator with 26.3dB SFDR and 7.5M BW at 1V

Author

Chen, J.Z. ; Xu, Z.T. ; Lim, W.M. ; Ning, N. ; Rong, L.M. ; Yu, Q. ; Liu, Y.

Author_Institution

State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China

fYear

2014

Firstpage

1

Lastpage

2

Abstract

This paper presents an architecture of flash analog to digital converters (ADCs) implemented with VCO-based comparators. The architecture reduce the power consumption of ADCs operating at high speed. The flash ADC is designed with 7 VCO-based compactors operating at 15MHz and simulated with CPPSIM. The signal to noise ratio (SNR), signal to noise and distortion ratio (SNDR), and spurious free dynamic range (SFDR) of the flash ADC are 17.5, 16.6 dB, and 26.3 dB, respectively with an input of 1MHz sine signal.

Keywords

analogue-digital conversion; comparators (circuits); voltage-controlled oscillators; CPPSIM; SFDR; VCO-based comparator; flash ADC design; flash analog-digital converters; frequency 15 MHz; power consumption reduction; signal-to-noise-distortion ratio; spurious free dynamic range; voltage 1 V; Flip-flops; Manganese; Noise; Phase frequency detector; Flash ADC; Ring Oscillator; VCO-based comparator; linearity; low voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on

Type

conf

DOI

10.1109/EDSSC.2014.7061144

Filename

7061144