Title :
A background jitter optimization method for PLL based on time-to-digital converter
Author :
Li, J. ; Liu, Y. ; Wu, S.Y. ; Ning, N. ; Yu, Q.
Author_Institution :
State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
A background jitter calibration method is proposed in this paper. It detects the RMS jitter by the jitter distribution based on time-to-digital converter (TDC). The jitter calibration is realized by regulating the loop bandwidth through the charge pump current. Simulation results show that the peak-to-peak jitter is reduced from 154.6ps to 24.1ps and the RMS jitter is reduced from 40.5ps to 5.8ps, respectively.
Keywords :
jitter; optimisation; phase locked loops; time-digital conversion; PLL; RMS jitter; TDC; background jitter calibration method; background jitter optimization method; charge pump current; jitter distribution; time-to-digital converter; Bandwidth; Calibration; Charge pumps; Clocks; Jitter; Noise; Phase locked loops; PLL; jitter; noise; time-to-digital converter;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
DOI :
10.1109/EDSSC.2014.7061146
