Title :
A novel clock duty cycle stabilizer
Author :
Xiaofeng Shen ; Xingfa Huang
Author_Institution :
Sci. & Technol. on Analog Integrated Circuit Lab., Chongqing, China
Abstract :
As ADCs improve to higher speed and resolution, A clock duty cycle stabilizer becomes more and more important. Improvement has been made in the proposed a clock duty cycle stabilizer circuit: a newly dynamic phase detector is designed to kill the dead working region; delay-limited cells are used to avoid false locking. The post-layout simulation shows that, working at 500MHz, the proposed clock stabling circuit can transform the duty cycle ranging from 10% or 90% to 50% with jitter smaller than 47fs, meeting the requirement of high speed ADCs.
Keywords :
analogue-digital conversion; circuit stability; clocks; delay lock loops; jitter; phase detectors; DLL; clock duty cycle stabilizer circuit; delay-limited cell; dynamic phase detector; frequency 500 MHz; high speed ADC; jitter; post-layout simulation; CMOS integrated circuits; Clocks; Detectors; Integrated circuit modeling; Logic gates; DLL; duty cycle; phase detector; pipeline ADC; styling;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
DOI :
10.1109/EDSSC.2014.7061148
