A novel clock duty cycle stabilizer

As ADCs improve to higher speed and resolution, A clock duty cycle stabilizer becomes more and more important. Improvement has been made in the proposed a clock duty cycle stabilizer circuit: a newly dynamic phase detector is designed to kill the dead working region; delay-limited cells are used to avoid false locking. The post-layout simulation shows that, working at 500MHz, the proposed clock stabling circuit can transform the duty cycle ranging from 10% or 90% to 50% with jitter smaller than 47fs, meeting the requirement of high speed ADCs.