An improved CMOS ring oscillator PLL applied in RapidIO communications

Author

Shanliang Gan ; Yuan Wang ; Song Jia ; Ganggang Zhang ; Xing Zhang

Author_Institution

Key Lab. of Microelectron. Devices & Circuits, Peking Univ., Beijing, China

fYear

2014

Firstpage

1

Lastpage

2

Abstract

A low jitter CMOS ring oscillator phase-locked loop (PLL) is presented in this paper. An improved voltage controlled oscillator (VCO) frequency control method is applied, and additional charge pump switches are used in the designed PLL. The VCO phase noise is -118.65dBc/Hz at 1 MHz offset from 3.125 GHz carrier, and the PLL total output jitter is 1.16ps at 3.125GHz in GlobalFoundries 0.13μm CMOS technology. The PLL locking time is 8μs and the total power dissipation with IO is 9.3mW.

Keywords

CMOS integrated circuits; charge pump circuits; frequency control; jitter; microwave oscillators; phase locked loops; voltage-controlled oscillators; GlobalFoundries 0.13μm CMOS technology; PLL; RapidIO communications; VCO frequency control method; charge pump switches; frequency 1 MHz; frequency 3.125 GHz; low jitter CMOS ring oscillator phase-locked loop; power 9.3 mW; size 0.13 mum; time 1.16 ps; voltage controlled oscillator frequency control method; CMOS integrated circuits; CMOS technology; Clocks; Control systems; Frequency control; Phase frequency detector; Voltage-controlled oscillators; RapidIO; low jitter; phase noise; phase-locked loop (PLL); voltage controlled oscillator (VCO);

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on

Type

conf

DOI

10.1109/EDSSC.2014.7061150

Filename

7061150