A 20 GHz PLL for 40 Gbps SerDes application with 4 bit switch-capacitor adaptive controller

This paper presents a high frequency PLL designed for 40 Gbps Serializer/Deserializer (SerDes). A 4 bit switch-capacitor is used to divide the tuning range by 16 and an adaptive controller is adopted to adjust the switch-capacitor automatically. In this way, the gain of the VCO would be reduced dramatically, so that the area of low pass filter could be reduced effectively while keeping the same loop bandwidth and out-band noise performance. Meanwhile, a pseudo differential charge pump with both common mode feedback and differential mode feedback is used to provide perfect in-band noise and spur. The PLL is implemented in 65 nm CMOS technology. The simulation result shows that the adaptive controller achieve the adaptive control of switch capacitor and adjust it to the proper value. The phase noise is -114.5 dBc/Hz @ 2.291 MHz and the spur is less than -86.7 dBc.