A multi-time frame scan test scheme for reduction of test time

Author

Guangyu Liu ; Zuolin Cheng ; Dongmei Xue

Author_Institution

Electron. Eng. & Comput. Sci., Peking Univ., Beijing, China

fYear

2014

Firstpage

1

Lastpage

2

Abstract

As system-on-chips grow in size and complexity, test application time in the scan chain increases rapidly. This paper proposes, based on the conventional scan test structure, a test method, MTFST(Multi-Time-Frame-Scan-Test), to solve the above problem. For this method, scan patterns, after applied to the scan chain, are propagated through the circuit under test for multiple timeframes and then shifted out for observation. We use elite genetic algorithm to generate initial MTFST vectors that have better fault detection characteristics. Experimental results on benchmark circuits show effectiveness of this scheme.

Keywords

automatic test pattern generation; benchmark testing; fault diagnosis; genetic algorithms; system-on-chip; benchmark circuits; fault detection; genetic algorithm; multitime frame scan test scheme; system-on-chips; test time reduction; Benchmark testing; Electrical fault detection; Fault detection; Genetic algorithms; Test pattern generators; Vectors; Multi-time-frame-scan-test; elite genetic algorithm; less test time; test pattern generation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on

Type

conf

DOI

10.1109/EDSSC.2014.7061157

Filename

7061157