A verification methodology for reusable test cases and coverage based on system verilog

As the size and complexity of SoC design grow, it is common to establish a scalable and reusable verification test bench for verification engineers. To improve the efficiency of verification and reduce the development time and effort in chip design projects, the extensive and reusable test case model and function coverage model for the special circuit and the standard protocols should be focused on by verification engineers. In this paper, a verification methodology for reusable test cases and coverage is described. As an example, a reusable test bench of chain table DUT is utilized to verify the feasibility of the verification methodology.