Title :
A threshold control technique for CMOS comparator design
Author :
Guoquan Sun ; Yin Zhang ; Lenian He ; Xiaolei Zhu
Author_Institution :
Inst. of Very Large Scale Integrated Circuits Design, Zhejiang Univ., Hangzhou, China
Abstract :
Area and power efficiency of ADC can benefit from the threshold configurable comparator based SAR ADC architecture. This work proposes a threshold control technique for CMOS comparator design with high linearity. One pair of binary weighted pMOS capacitor arrays is used to generate the built-in threshold levels; another pair of digitally switched pMOS capacitor arrays is implemented to compensate the nonlinearity for the generated threshold levels. The simulation results show the range of the controlled threshold is 260mV. 6-bit resolution with 0.6 LSB INL and 0.25 LSB DNL are achieved. The comparator consumes 5.0μW with 30MHz clock frequency from 1.8V power supply.
Keywords :
CMOS digital integrated circuits; MOS capacitors; analogue-digital conversion; comparators (circuits); integrated circuit design; CMOS comparator design; binary weighted pMOS capacitor arrays; built-in threshold levels; digitally switched pMOS capacitor arrays; frequency 30 MHz; generated threshold levels; power 5.0 muW; threshold configurable comparator based SAR ADC architecture; threshold control technique; voltage 1.8 V; voltage 260 mV; word length 6 bit; CMOS integrated circuits; CMOS technology; Capacitance; Capacitors; Clocks; Linearity; Threshold voltage; CMOS; Comparator; Threshold control;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
DOI :
10.1109/EDSSC.2014.7061169
