A threshold control technique for CMOS comparator design

Area and power efficiency of ADC can benefit from the threshold configurable comparator based SAR ADC architecture. This work proposes a threshold control technique for CMOS comparator design with high linearity. One pair of binary weighted pMOS capacitor arrays is used to generate the built-in threshold levels; another pair of digitally switched pMOS capacitor arrays is implemented to compensate the nonlinearity for the generated threshold levels. The simulation results show the range of the controlled threshold is 260mV. 6-bit resolution with 0.6 LSB INL and 0.25 LSB DNL are achieved. The comparator consumes 5.0μW with 30MHz clock frequency from 1.8V power supply.