Title :
A 6.25Gb/s CMOS clock and data recovery DLL with anti-harmonic lock
Author :
Yuequan Liu ; Yuan Wang ; Song Jia ; Ganggang Zhang ; Xing Zhang
Author_Institution :
Key Lab. of Microelectron. Devices & Circuits (MoE), Peking Univ., Beijing, China
Abstract :
This paper presents a clock and data recovery (CDR) delay locked loop that operates in high frequency while keeping low jitter performance. The data rate can be twice the reference clock frequency. A self-starting-control circuit widens the phase capture range. In order to compensate for the attenuation of channel, an equalizer comprised of two peaking amplifiers is employed in front end of CDR. The circuit is implemented in SMIC 1.2V 65nm CMOS technology. It demonstrates that at 6.25Gb/s data with -20dB attenuation, the periodic jitter of the recovery clock is 14.08ps for a total power consumption of 6.5mW.
Keywords :
CMOS integrated circuits; clock and data recovery circuits; delay lock loops; jitter; CDR delay locked loop; SMIC CMOS technology; anti-harmonic lock; bit rate 6.25 Gbit/s; clock and data recovery DLL; low jitter performance; peaking amplifiers; periodic jitter; power 6.5 mW; power consumption; reference clock frequency; self-starting-control circuit; size 65 nm; time 14.08 ps; voltage 1.2 V; CMOS integrated circuits; CMOS technology; Clocks; clock and data recovery (CDR); delay-lock loop (DLL); harmonic lock; high speed; wide frequency range;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
DOI :
10.1109/EDSSC.2014.7061227
