Using nonvolatile processors to reduce leakage in power management approaches

Over the last few years, static energy(mainly induced by leakage current) has dominated a large portion of total energy consumption in chips. Although power management approaches have been used to reduce active power, they are ineffective in reducing static power when applied in normal volatile processors. In this paper, we explored the usage of nonvolatile processors(NVPs), which are able to maintain states during power failures, to reduce leakage power in power management approaches. We evaluated several existing power management strategies and experimental results show that using NVPs in the leakage-aware power management is able to save 15% extra energy and achieve 30% more static energy savings compared with volatile processors.