Critical parasitic capacitance in nano-scale phase-change memory (PCM) cell

Parasitic capacitances of phase-change memory (PCM) bitlines which induce RC delay lead to reset failure. To analyze the critical parasitic capacitance of different feature sizes, the transient resistances of PCM cells with different geometries during programming is to be evaluated. In this work, an accurate numerical model including latent heat comparison (LHC) which is able to calculate transient resistance is developed, and a AlST-based PCM cell is simulated. Combining the transient resistance and the periphery parasitic circuit, the impact of the fall time during the end of reset pulse induced by parasitic capacitances is simulated. Results show that reset failure may happen during device scaling down. The method can be used to predict critical parasitic capacitance and critical size of PCM cells with different materials or structures.