Chip design of low-power phase-locked loop for FMCW MMW radar and sensor application

A 24 GHz phase-locked loop (PLL) with a LC-tank voltage-controlled oscillates (VCO) is implemented in TSMC 90 nm CMOS for FMCW MMW radar and sensor application In this proposed circuit including a cross-coupled Colpitts VCO is adopted to decrease the transistor parasitic capacitance and reduce the phase noise. Second, an injection locked frequency divider (ILFD) is utilized in first divider stage to handle the high frequency signal. Measured results achieve that at supply voltage of 1.2 V, the VCO output frequency is tunable and the synthesizer phase noise is about -97.47 dBc/Hz at 1MHz offset from the carrier frequency. The mixed output power spectrum is -2.97 dBm at 10.2 GHz and the power consumption is 9.24 mW.