FPGA implementation of fast and area efficient CORDIC algorithm

This paper presents the fast and area efficient CORDIC (Coordinate Rotation DIgital Computer)algorithm for sine and cosine wave generation. The concepts of pipelining and multiplexer based CORDIC algorithm is used todecrease the critical path delay and reducing the area respectively. A six stage CORDIC is implemented by two schemes followed by four methods, unrolled CORDIC and multiplexer based CORDIC with and without pipelining. The pipelining is included in four stages(excluding first and last stage). An 8-bit CORDIC algorithm for generating sine wave and cosine wave is designed, implementedand compared by all four methods on Xilinx Spartan3E (XC3S250E).