FPGA implementation of fast and area efficient CORDIC algorithm

Author

Chinnathambi, M. ; Bharanidharan, N. ; Rajaram, S.

Author_Institution

Dept. of Electron. & Commun., Thiagarajar Coll. of Eng., Madurai, India

fYear

2014

Firstpage

228

Lastpage

232

Abstract

This paper presents the fast and area efficient CORDIC (Coordinate Rotation DIgital Computer)algorithm for sine and cosine wave generation. The concepts of pipelining and multiplexer based CORDIC algorithm is used todecrease the critical path delay and reducing the area respectively. A six stage CORDIC is implemented by two schemes followed by four methods, unrolled CORDIC and multiplexer based CORDIC with and without pipelining. The pipelining is included in four stages(excluding first and last stage). An 8-bit CORDIC algorithm for generating sine wave and cosine wave is designed, implementedand compared by all four methods on Xilinx Spartan3E (XC3S250E).

Keywords

digital arithmetic; field programmable gate arrays; pipeline processing; FPGA implementation; XC3S250E; Xilinx Spartan3E; area efficient CORDIC algorithm; coordinate rotation digital computer; cosine wave generation; multiplexer based CORDIC; multiplexer based CORDIC algorithm; pipelining concepts; sine wave generation; unrolled CORDIC; Algorithm design and analysis; Clocks; Delays; Field programmable gate arrays; Multiplexing; Pipeline processing; Vectors; CORDIC algorithm; FPGA; Multiplexer; Pipelining; Sine/Cosine; Unrolled CORDIC;

fLanguage

English

Publisher

ieee

Conference_Titel

Communication and Network Technologies (ICCNT), 2014 International Conference on

Print_ISBN

978-1-4799-6265-5

Type

conf

DOI

10.1109/CNT.2014.7062760

Filename

7062760