An efficient implementation of 2-D discrete wavelet transform for high speed DSP applications

This paper presents an efficient VLSI architecture of a high speed, low power two dimensional Discrete Wavelet Transform (2-D DWT). The proposed work minimizes the resource requirement and complexity of system. Design modules were realized using basic wavelet in HDL language and MATLAB for optimizing the speed and memory requirements. The system is modeled and implemented using Xilinx VirtexE FPGA device. The simulation results obtained through Mentor graphics simulation software. The system computing rate is up to 290 M samples/s and design uses only 34.376ns combinational path delay for 8×8 image size. In this way, the developed design provides very high-speed processing.