Low power and high speed row and column bypass multiplier

The demand for electronic portable devices is gaining more attention in recent decades. Portable devices are demanding for low power. Multiplier is the critical part of any arithmetic operation in many DSP applications. So it is essential to design multipliers that utilize less power and provide high speed of operation. One main aspect of low power design is to minimize switching activities to reduce dynamic power dissipation. So the proposed bypassing logic will reduce Dynamic power dissipation as well as signal propagation delay. Row and column bypass multiplier is a new design which reduces the switching activities with architecture optimization. The switching activity should not occur unnecessarily and it should be avoided by bypassing. The adders corresponding to those rows or columns which are required to be bypassed, need not be activated and signal get bypassed to the further stage. With the help of tri-state buffer as a control gating element, unnecessary signal propagation can be stopped. Thus, the unwanted switching activity can be reduced. The proposed multiplier design is efficient in terms of power by 20% or more when probability of occurrence of zeros is more. These features make the proposed design more suitable for DSP applications like filtering, Discrete Cosine Transform (DCT) and Fast Fourier Transform (FFT).