A SRAM design based on tetrad and hierarchical dynamic decoding technology

Static random access memory (SRAM) is a type of static access memory which employs latching circuitry to store data. It can save the data without refreshing logic circuit. In order to obtain a high speed and low power consumption SRAM, the layout of the memory array is critical. A new SRAM structure is analyzed and proposed in this paper. The proposed design uses tetrad technology and hierarchical dynamic decoding technology. The whole capacity of the proposed SRAM is 64*256 bits, and distributed in the four corners of the chip. Decoding circuit is symmetrical, and divided into the low 32-bit and high 32-bit. Compared to the traditional decoding circuit, it has faster speed, more compact structure, and smaller size.