Title :
10-T Full Subtraction Logic Using GDI Technique
Author :
Singh, Haramardeep ; Kumar, Rajat
Author_Institution :
Sch. of Electron. & Commun., Lovely Prof. Univ., Jalandhar, India
Abstract :
Circuit designing using CMOS logic is the promising field for VLSI engineers, but with demand of small and portable devices, new techniques for low power are emerging. This paper proposed four different 10-T subtraction logic using Gate Diffusion Index (a new technique for low power design). Simulation results are performed using 180nm technology using Cadence Virtuoso. Complete verification for performance of proposed subtraction logic is carried and circuit with least power and delay has been reported. Layout design for the best optimum ciruit is designed using Cadence Layout XL.
Keywords :
CMOS logic circuits; integrated circuit layout; low-power electronics; 10-T full subtraction logic; CMOS logic; Cadence Virtuoso; Cadence layout XL; GDI technique; VLSI engineers; circuit design; gate diffusion index; layout design; low power design; portable devices; small devices; CMOS integrated circuits; CMOS technology; Delays; Layout; Logic gates; Multiplexing; Transistors; CMOS; Delay; Full Subtractor; GDI (Gate Diffusion Index); Low power design;
Conference_Titel :
Computational Intelligence and Communication Networks (CICN), 2014 International Conference on
Print_ISBN :
978-1-4799-6928-9
DOI :
10.1109/CICN.2014.202
