Title :
Design of High Performance IEEE754 Floating Point Multiplier Using Vedic Mathematics
Author :
Mahakalkar, Sushma S. ; Haridas, Sanjay L.
Author_Institution :
GHRAET, Nagpur, India
Abstract :
The fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and the speed of the DSPs is mainly determined by the speed of its multiplier. In this paper we have synthesized and verified IEEE 754 single and double precision High Speed Floating Point Multiplier using VHDL on Xilinx Virtex - 5 FPGA. The Urdhva-Tiryakbhyam sutra (method) was selected for designing of mantissa. In addition the proposed designed handled underflow, overflow and rounding condition. High speed is achieved by reducing carry propagation delay by using carry save adder while implementation of four (27 × 27 bit multiplier for double precision) and (12 × 12 bit multiplier for single precision).
Keywords :
IEEE standards; field programmable gate arrays; floating point arithmetic; hardware description languages; multiplying circuits; UrdhvaTiryakbhyam sutra; VHDL; Vedic mathematics; Xilinx Virtex - 5 FPGA; carry propagation delay reduction; carry save adder; high performance IEEE754 floating point multiplier; high speed floating point multiplier; mantissa design; overflow condition; rounding condition; underflow condition; Adders; Algorithm design and analysis; Digital signal processing; Propagation delay; Signal processing algorithms; Standards; Urdhva-Tiryakbhyam sutra; VHDL;
Conference_Titel :
Computational Intelligence and Communication Networks (CICN), 2014 International Conference on
Print_ISBN :
978-1-4799-6928-9
DOI :
10.1109/CICN.2014.207
