DocumentCode
3581621
Title
A V-band CMOS 90nm PLL
Author
Chung, Yun-Rong ; Yu, Yueh-Hua ; Lu, Yun-Chih ; Chen, Yi-Jan Emery
Author_Institution
Graduate Institute of Electronics Engineering and Graduate Institute of Communication Engineering, National Taiwan University, Taipei 10617, Taiwan
fYear
2014
Firstpage
1259
Lastpage
1261
Abstract
This paper presented a V-band phase-locked loop implemented in 90-nm standard CMOS process. The capacitor bank switching techniques is adopted to increase the VCO tuning range. The VCO´s band switching is controlled by the 3-bit digital control circuit. To ensure oscillating at low frequency band, the bias current is adjusted with respect to oscillation frequency. The proposed PLL operates form 39.54 – 43.38 GHz. The measured reference spur is −50.61dBc, and the phase noise is −92 dBc/Hz form 1MHz frequency offset.
Keywords
CMOS integrated circuits; Electronic mail; Frequency conversion; Phase locked loops; Tuning; Voltage-controlled oscillators; Wireless communication; Frequency synthesizer; PLL; V-band;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Conference (APMC), 2014 Asia-Pacific
Type
conf
Filename
7067630
Link To Document