A fully integrated CMOS broad band power amplifier using a low-Q matching strategy

A fully integrated CMOS broadband power amplifier in 0.18µm technology is presented using a unique combination of a cascode output stage, low-Q single section L-match networks and inter-stage degeneration. Matching sections are implemented with bias feed inductors and dc blocking capacitors to minimize the active chip area to 0.55 mm². The proposed design, achieves a fractional bandwidth of 82 % in bare die measurements, where maximum power at saturation of + 17.3 dBm with a variation of ±1 dB and a peak drain efficiency of 34% with a variation of ± 2% over the band are achieved. A fractional BW of 59% is also noted from the measurement of a QFN packaged version.