Analytical model of voltage division inside stacked-FET switch

An analytical model of the voltage division inside a MOSFET stack is presented. The voltage division can be described by a simple closed-form analytical expression. This approach provides not only a much faster calculation, but also a more clear understanding of the influence of single FET parameters on the FET stack behavior. Analytical expressions for the off capacitance (Coff) and breakdown voltage (BV) of a FET stack are then derived. By increasing the number of the stacked FETs, a minimum Coff and a maximum BV are predicted. The analytical model is validated against both numerical calculation and measurements.